A 100-Gbps low-power PRBS generator based on a half-rate-clock architecture using InP HBTs

A new architecture using a half-rate clock for pseudo-random-bit-sequence (PRBS) generator has been devised for high-speed and low-power operation. For proof of concept, a 2
⁷
-1 PRBS generator IC was designed and fabricated with 290-GHz-f
_T
InP HBT technology. The PRBS generator operates up to 100 Gbps with a low power consumption of 955 mW, leading to a record figure-of-merit of 1.42 mW·Gbps
^-1
. This circuit can provide a clear waveform with a very low RMS jitter of less than 500 fs in the whole operation range.