Low static and dynamic power MTCMOS based 12T SRAM cell for high speed memory system

This paper focuses on the static and dynamic power dissipations and power delay product of a proposed novel low power MTCMOS based 12T SRAM cell. In the proposed structure two voltage sources are used, one connected with the Bit line and the other one connected with the Bit bar line in order to reduce the swing voltage at the output nodes of the bit and the bit bar lines. Reduction in swing voltage causes the reduction in dynamic power dissipation during switching activity. Because of MTCMOS technology, the SRAM cell is having low V
_T
(LVT) transistors and there are two high V
_T
(HVT) sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static power dissipation of the SRAM cell. Simulation results of static and dynamic power dissipations and power delay product of the proposed SRAM cell have been determined and compared to those of some other exiting models of SRAM cell. The proposed SRAM cell dissipates less dynamic power at different frequencies, less static power during transition modes. Simulation has been done in 45nm CMOS environment with the help of Microwind 3.1.