Accurate modeling of dynamic variability of SRAM cell in 28 nm FDSOI technology

The paper presents a new methodology to model the dynamic variability of SRAM cell in 28nm FDSOI technology. This approach can be easily integrated into SPICE and used for circuit degradation simulation. It is based on two successful models that showed good correlation with experimental data. Using only stress measurements made at transistors level we are able to simulate the degradation obtained on SRAM circuit level. Based on this methodology, fast BTI stress measurements were carried out on SRAM-sized MOSFETs using a fast measure/stress/measure sequences. Using these measurements at transistor level we could validate our modeling methodology by comparing this analytical approach to experimental data. Finally, simulations results obtained on a 0.197 μm
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SRAM cell and calibrated to pull-up and pull-down stress measurements are presented. The bit-cell read margin is evaluated using the Supply Read Retention Voltage (SRRV) metric and resulting ΔSRRV cumulative distributions obtained from 4000 MC simulations are shown.