A low voltage inverter-based continuous-time sigma delta analog-to-digital converter in 65nm CMOS technology

In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.