9.9-mA 5–6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5–6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.