Method for back-annotating per-transistor power values onto 3DIC layouts to enable detailed thermal analysis

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large spikes in individual device temperatures. These “hotspots” must be carefully analyzed at design time to ensure that the device temperatures will not cause the circuit to malfunction, and to assess the device temperature's impact on the longevity of the circuit. In this paper we present a tool flow for capturing accurate per-transistor power values in standard cell designs to allow for detailed thermal analysis. After extracting power values, High Definition Power Blurring is used to analyze the thermal performance of the inter-chip communication bus of a “Cool Interconnect” chip.