Pixel detector readout electronics with two-level discriminator scheme

In preparation for a silicon pixel detector with more than 3000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog frontend of the readout electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.81 /spl mu/m process but compatible with the design rules of the radiation hard Honeywell 0.8 /spl mu/m bulk process. Each cell contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 /spl mu/m by 140 /spl mu/m. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900 mV for a minimum ionizing particle (MIP, about 24000 e/sup -/ for a 300 /spl mu/m thick Si-detector) with a return to baseline within 750 ns for a 1MIP input signal. The full readout chain (without detector) shows an equivalent noise charge of 60 e/sup $/r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22 ns at a separation of 1500 e/sup -/, which is adequate for the 40 MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40 fF coupling capacitance, is less than 3%. A single cell consumes 35 /spl mu/W at 3.5 V supply voltage.