An FPGA-based digital predistorter for RF power amplifier linearization using cross-memory polynomial model

A cost-effective and flexible FPGA-based system architecture for digital predistortion (DPD) based linearization of power amplifiers (PAs) is proposed. The system is used to show the effectiveness of the cross-memory polynomial model (CMPM) for DPD. Two commercial amplifiers are linearized using single and two-carrier Wideband Code Division Multiple Access (WCDMA) signals as excitation and the performance of CMPM for DPD is compared to those of the memory polynomial (MPM) and memoryless models (MLM).