Hardware-Oriented Construction of a Family of Rate-Compatible Raptor Codes

A family of architecture-aware Raptor codes is constructed. The proposed construction scheme is targeted to design rate-compatible structured codes that span a wide range of rates and block sizes while still having hardware-efficient decoder implementations. The codes match the corresponding fixed-rate LDPC codes in error-correcting performance, decoding convergence speed, and message-memory requirements. Three novel steps are incorporated in the scheme: 1) a new group-based design of the code source matrix; 2) an architecture-aware row splitting-after-merging technique to construct irregular precodes; and 3) structured LT row-encoding. A code instance was designed accordingly and compared to standardized LDPC codes. The error-rate performance closely matches that of LDPC, whereas the convergence speed and message count gaps are narrowed down to values between
$[1.1\times, 1.8\times]$
and
$[1.1\times, 1.3\times]$
, respectively.