The underfill-microbump interaction mechanism in 3D ICs: Impact and mitigation of induced stresses

3D IC assembly processes are introducing new stress mechanisms not observed in 2D environments, which have significant effects on the performance of both BEOL and FEOL. This paper deals with the underfill-microbump interaction mechanism observed after 3D IC stacking and focuses on its scarcely explored impact on the FEOL. FEOL stress sensors and finite element models are employed to analyze the interaction mechanism development on manufactured 2-tier stack test vehicles - memory on 130nm node logic die and 32nm node logic on logic dies. The logic dies vary from 25 to 50 nm in thickness with a thick memory die on top. 3D IC stacking stress reduction design guidelines are established for Si dies, underfill and microbumps such as die thickness, backside passivation, microbump diameter, pitch, height, and underfill Young's modulus, CTE and glass transition temperature. Furthermore, the equivalent zero stress stack bonding temperature and stress build up above underfill glass transition temperature is analyzed. Stress sensor evaluation methodology and stress impact on FEOL devices - planar and FinFETs is briefly discussed within the scope of the topic.