A genetic algorithm for multiple fault model test generation for combinational VLSI circuits

The authors present a genetic algorithm (GA) for the automatic generation of test vector-pairs for the detection of both delay and single stuck-at-fault models in combinational digital VLSI circuits. The GA proves effective in searching the highly complex problem space, which is significantly larger than that with single stuck-at-faults only. The paper describes the GA and results obtained for the ISCAS 1985 benchmark circuits. The initial concept of transitional test pattern generation using a basic GA was introduced by the authors previously.