A novel soft error immunity SRAM cell

The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.