A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

This brief describes the design of a four-channel 32-Gb/s serial link transmitter with a current-recycling output driver and an on-chip ac-coupled receiver. The proposed output driver significantly reduces power dissipation in the final stage of the transmitter by reusing the natural current flow through the four-channel outputs. It also eliminates the voltage regulation circuit and the current source circuitry for generating low-swing outputs. Since the four-channel outputs are stacked from the ground to the supply rail with different common-mode output levels, the receiver should include an ac-coupling circuit to establish the desired common-mode voltage level for the receive amplifier in each channel. A long-time constant is realized in the ac-coupling circuit with small on-chip capacitors. The prototype chip has been fabricated in the 65-nm low-power CMOS process, and the transmitter supports an output swing of 300
$\hbox{mV}_{{\rm pp}, \,{\rm diff}}$
at a data rate of 8 Gb/s. The four stacked output drivers only consume a total static power of 1.8 mW, and the overall transceiver, including an equalization of 7 dB, exhibits a normalized power dissipation of 2.04 mW/Gb/s.