An Asic Implementation Of An Optimized Digital Video Encoder

This paper presents a design of an optimized video encoder by using a pipelined architecture of multiplierless structures. The proposed video encoder accepts conventional NTSUPAL video signals. It also processes the PAL-plus video signal, which is popular in Europe. The proposed encoder requires only 25k gates, which is a 40% reduction in hardware compared with conventional systolic pipelined architecture. The overall performance has been verified by using 0.65μ m CMOS process.