Towards 100G packet processing: Challenges and technologies

Driven by media-rich and bandwidth-intensive Internet applications, 100 Gigabit Ethernet embodies the next logical and necessary line speed following 10G/40G, although enormous challenges exist. Can today's device technologies scale, or will new, disruptive approaches be required to overcome throughput and power density limitations? The evolution of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technology was analyzed concerning speed, density, power, and pin interfacing. While clock frequencies cannot keep up with the higher interface speeds, massive parallelism and deep pipelining are needed to scale the throughput. The state-of-the-art architectures and algorithms for every aspect of packet processing are described. In addition, we look at alternative memory concepts and cover some emerging technologies: asynchronous FPGAs as a means for boosting the system clock and serial interfaces reducing the pin count between devices. Thereby, economic considerations limit the choice between the options. We conclude that although significant effort is necessary in terms of device and board technology, economic 100G networking is viable.