A residue to binary converter for a balanced moduli set {22n+1 − 1, 22n, 22n − 1}

In this paper, we propose a new moduli set {2
²ⁿ⁺¹
- 1, 2
²ⁿ
;2
^{2n - l}
} with its associated reverse converter. The proposed reverse converter is based on Mixed Radix Conversion (MRC). In addition to parallelizing and optimizing the MRC algorithm, the resulting architecture is further simplified in order to obtain a reverse converter that utilizes only 2 levels of Carry Save Adders and three Carry Propagate Adders. The proposed converter is purely adder based and memoryless. Our proposal has a delay of (10n + 4)t
_fa
+ 2t
_mUx
with an area cost of (12n + 2)FAs and (2n)H As, which when expressed in terms of HA is (22n + 4), where FA, HA, and t
_fa
represent Full Adder, Half Adder, and delay of a Full Adder, respectively. The proposed scheme is compared with state of the art similar dynamic range converters. Theoretically speaking, our proposal achieves about 62.3% hardware reduction and about 2.13% speed improvement when compared with the reverse converter for {2
ⁿ
+ 1,2
ⁿ
1, 2
²ⁿ⁺¹
- 3, 2
²ⁿ
- 2}. Also, in comparison with the converter for {2
ⁿ
- 1, 2
ⁿ
- 1, 2
²ⁿ⁺¹
- l}, the results indicate that, our proposal is about 17.05% faster, but requires about 7.83% more hardware resources. Further, the area time square (Δ
_T
²
) metric indicates that our proposed converter is 62.3% and 24.77% better than the state of the art reverse converters for {2
ⁿ
+ 1,2
ⁿ
- 1, 2
²ⁿ⁺¹
- 3, 2
²ⁿ
- 2} and {2
ⁿ
- 1, 2
ⁿ
+ 1, 2
²ⁿ
, 2
²ⁿ⁺¹
- l} respectively.