A low power and high speed level shifter with delay circuits

A level shifter with low power and high speed characteristics is proposed, which is simulated in the 0.18μm standard CMOS process. The proposed level shifter minimizes the contention problem between the pull-up PMOS transistors and pull-down NMOS transistors by using delay circuits. Compared with the conventional level shifter, the simulation results show that the proposed level shifter can achieve about 42.8% power reduction, 6.7% falling time of output level signal saving and 20.0% high-to-low propagation delay speed-up for the output load capacitance in the range of 0.2pF to 2pF when converting 1.8V to 3.3V. Besides, the proposed level shifter has about 38.4% improvement in the overall performance. Hence, the proposed level shifter is suited for low power, high speed applications.