Low power noise tolerant domino 1-bit full adder

A new low power dynamic CMOS one bit full adder cell is presented in this paper. In this design technique is based on semi-domino logic. This new adder cell was compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay product and leakage performance of low voltage full adder cells in different CMOS logic styles. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP, and noise tolerance. The performance of the adder circuits is based on UMC 180nm CMOS process models at the supply voltage of 1.8V evaluated by the comparing of the simulation results obtained from Cadence specter. Simulation results tell that the proposed circuit exhibits a lower PDP and is faster when it was compared with available 1-bit full adder circuits.