Study of thermal stress by numerical simulation method on electronic package with power chip

According to simulation results of the temperature, thermal stress of electronic package is analyzed by thermal-mechanical sequential coupling method. The results show that higher thermal stress are located in the place around power chip when the stress neighboring the periphery of the package is lower and the maximum thermal stress locates at the contact site between the cover and the substrate. By altering simulation parameters of electronic package, such as using higher thermal conductivity cover materials to improve thermal conductivity, reducing the thickness of adhesive and enhancing convection coefficient, thermal stress could be effectively reduced. Numerical simulate results provide theoretical basis for reducing thermal stress and optimizing the electronic packaging structure.