Dynamic queue assignment in a VC queue manager for gigabit ATM networks

Today, ATM networks are being used to carry bursty data traffic with large and highly variable transmission rates, and burst sizes ranging from kilobytes to megabytes. Obtaining good statistical multiplexing performance for this kind of traffic requires much larger buffers than are needed for more predictable applications or for bursty data applications with more limited burst transmission rates. Large buffers lead to large queueing delays, making it necessary for switches to implement more sophisticated queueing mechanisms in order to deliver acceptable quality of service (QoS). This paper describes a 2.4 Gb/s ATM queue management chip that has practically unlimited buffer scaling and also supports dynamic per VC queueing, an efficiently implementable form of weighted round-robin scheduling, a novel packet-level discarding algorithm and the ability to support multiple output links. We give a detailed description of the dynamic queue assignment mechanism, which allows the chip to support both virtual path and virtual circuit channels. This mechanism is self-configuring, eliminating the need to configure the range of VCIs associated with a given VPI, and makes optimal use of the chip's per-channel data structures, since these data structures can be assigned only when cells are present in the queues.