Design of low power pulsed flip-flop using sleep transistor scheme

In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm low clock load dynamic flip-flops, a novel sleep transistor scheme is proposed. The scheme is implemented using CMOS 90nm technology file in Synopsis HSPICE. As compared to the conventional pulse triggered flip-flops, the proposed sleep transistor based P-FF design features best power-delay-product performance. The average power and leakage power is reduced without degrading the overall performance.