Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform

In this paper, a hardware efficient lifting based parallel 3-D Discrete Wavelet Transform (DWT) architecture for infinite group of pictures is proposed. Two parallel spatial and temporal DWT modules of the proposed 3-D DWT architecture give high throughput of 4 results per clock cycle. 1-D DWT blocks are employed for the spatial and temporal processing, respectively. Two parallel spatial processors reduce the requirement of frame memory for temporal transformation. Higher throughput reduces the working clock cycles which leads to low power design. A novel dual scanning in Z-fashion is utilized to reduce the internal transpose buffer requirement and waiting time of both the column and the temporal processors. The comparison results show that the internal memory requirement of the proposed 3-D DWT architecture is smaller than other familiar architectures. The Register Transfer Logic (RTL) of the proposed design is described using VHDL and synthesized for the Xilinx Virtex-IV series field programmable gate array (FPGA). The RTL of the proposed design is also synthesized using UMC 180 nm technology CMOS standard cell library for Application Specific Integrated Circuit (ASIC) design.