Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices

Summary form only given, as follows. The push for portable, battery-operated, and “cool-and-green” electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and lowpower test generation). Physically-aware low-power test techniques are also becoming important for accuracy and hot-spot minimization, especially for designs at 22nm and below. Furthermore, with power optimization and power management techniques becoming “de-facto” in almost all 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an in-depth and up-to-date understanding of low-power IC testing covering (a) dimensions of power-aware testing, (b) methods for test power analysis and signoff, (c) techniques for controlling test power consumption and (d) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will be outlined to illustrate capabilities and gaps in the state-of-the-art.