A modified CDMA scheme based NOC architecture for complex SOC applications

The complexity of System-On-Chip (SOC) design is increasing continuously due to the multidimensional optimization requirements, while integrating complex intellectual property (IP) blocks. The interconnectivity topologies between IPs are playing a vital role in deciding the performance of the SOCs. This paper investigates the existing code division multiple access (CDMA) based network on chip (NOC) architectures. The work presented here explains a variant of CDMA based NOC scheme, which is best suitable at the base band level implementation for dynamic bandwidth management. A six node globally-asynchronous locally-synchronous (GALS) type NOC is realized at RTL level, with two different controller architectures. Both vary in terms of key management and control mechanism. The scheduler-built-in-ring type architecture, with its ease in placement and routing is suitable for complex SOCs. The architectures are implemented in VHDL and verified at simulation level. The Xilinx FPGA synthesis results promise more than 200 MHz clock speeds resulting in 1.6 Gbps data throughput over 32 bit ring bus on Virtex-6 LX series FPGAs.