Robust, ultra fast data sensing technique for low power asymmetrical SRAM with self-shut-off feature

Single ended data sensing for asymmetrical low voltage memories has become a topic of much interest due to its application in very low energy computing and communication. In this paper, we present an ultra-high-speed (UHS) data sensing scheme for single ended near threshold asymmetric static random access memory (SRAM) design in a 45nm standard CMOS process. The proposed bit-line decoupled single ended sense amplifier (BD-SESA) deactivate a low-V
_th
latch by fixing the gate of NMOS device to ground (gnd) which makes the proposed scheme vulnerable to wrong latching for bitline offset due to process variation. We rigorously investigated the impact of process, voltage and temperature (PVT) variation on sensing delay, standby leakage and sensing failure and achieved commendable improvement in power dissipation and sensing delay. A self shut-off mechanism (SSM) significantly reduces voltage swing at read bit-line (RDBL) which further results in reduced power dissipation. Extensive post-layout simulation has verified that our design is insensitive to bit-line capacitance and achieves sensing delay of 297.7pS and 411.7pS at 1V and 0.8V supply respectively and offers 52.56% and 60.36% better mean with 61. 3% and 19.7% less silicon area than designs in comparison.