Design of variation-resilient CNFET-based Schmitt trigger circuits with optimum hysteresis at 16-nm technology node

Process, voltage and temperature (PVT) variations in emerging ultra-deep submicron (UDSM) technology nodes critically affect device performances and limit further scaling of such devices based on Moore's law. This paper proposes CNFET-based design of robust Schmitt trigger circuits, which outperform their CMOS counterparts in terms of mean values as well as variabilities of all considered design metrics. Popular Schmitt trigger designs are investigated and a comparative analysis is carried out based on Monte Carlo simulations in an HSPICE environment, using the 16-nm CMOS Predictive Technology Model (PTM), to choose the designs with best performance in terms of variability of design metrics such as power, power-delay product (PDP) and hysteresis width. These are then re-designed with corresponding optimized devices using the experimentally validated Stanford University CNFET model. The proposed CNFET-based circuits provide a 9.9×, 11.8× and 22× improvement in power, PDP and hysteresis width variability respectively, while also providing better noise immunity through increased hysteresis widths, thus demonstrating their superiority to CMOS circuits in all respects at highly scaled technology nodes.