A 833 Mb/s 2.5 V 4 Mb double data rate SRAM

A double-data-rate (DDR) SRAM overcomes the limitation of a single-data-rate (SDR) SRAM. The main features are an auto-tracking bitline scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, a two bit pre-fetched operation, and strobe clocks synchronized with the output data to guarantee CPU data-validation time.