A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier

This microprocessor is optimized for the desktop. The chip contains architectural, circuit, and technology enhancements that include a 32 kB, 2-way set associative virtual instruction cache, a 16 kB, dual-read-ported, physical data cache, and advanced branch prediction. Circuit enhancements include a 6.0 ns integer multiplier, a 19.5 ns floating-point divider, and to support low jitter, 50% duty cycle 667 MHz clock, and an on-chip PLL. The 5.7M transistor microprocessor is fabricated in a 2.0 V, 0.28 /spl mu/m CMOS process with 4-layers of metal for interconnect, measures 1.0 cm/sup 2/, and supports a 2.5 V interface.