Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

The characterization of vertical poly-Si transistors, important for optimizing vertical SONOS memory configurations, is studied by means of a resistive network model. The statistical variation of the I
SD
-V
G
characteristics allows to extract the poly-Si grain size and from the sub-threshold regime information on the energy distribution of the poly-Si defects is extracted. This model indicates the separated impact of interface states and poly-Si states on current and V
th
.