Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., I
_ON
, I
_OFF
, V
_th
, SS, R
_C
) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔV
_th
, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.