Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

We present gate all around strained Si (sSi) nanowire array TFETs with high I
_ON
(64μA/μm at V
_DD
=1.0V). Pulsed I-V measurements provide small SS and record I
₆₀
of 1×10
^-2
μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I
_ON
. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.