Correlation of PDN impedance between measurements and simulation of 3D-SiP

Recently, ultra-wide bus 3D-SiP with TSV's has attracted great attention to achieve energy-saving and high-performance system level module. TSV technology is a new technology of vertical wiring to make shorter than the conventional wire bonding. However, the power supply integrity and signal integrity has become an issue due to the increase of simultaneous switching output buffers. In this paper, PDN impedances of 3D-SiP were examined by the measurement and simulation. Simulated PDN impedances of three chips were well correlated with the measured results.