A toolset for easy development of test and repair infrastructure for embedded memories

The development of a modern System-on-Chip (SOC) requires usage of embedded IP blocks from different vendors. One of widely used IP blocks in SOC is an embedded memory that usually occupies an essential die area. All IP blocks can have manufacturing defects. Meanwhile, in difference to other SOC components embedded memories are more defect-prone. STAR Hierarchical System (SHS) is an infrastructural IP solution for built-in test and repair engines of IP blocks. It is widely adopted now by a variety of customers which development flows essentially differ from each other. To cover the diversity of requests for user maintenance implying from difference in development flows we suggest a new approach basing on a library of SHS standard use flows implemented in a form of templates and a special toolset for their modification and verification. The implemented library of templates assists to design new flows quickly through retrieving and customizing specific examples. User can extend the library via insertion of new templates. A formal verification approach used already for business processes is successfully applied to the built library. The application is illustrated on some use flow examples.