Memory-centric architectures: why and perhaps what

Summary form only given. Distributing processors to regions of memory necessitates partitioning the problem and decomposing the data to the partitioned regions. Both can be hard to do well statically; some codes lend themselves well to one or both, while others are not amenable to static analysis. If the problem partitioning does not match the data decomposition, extremely poor program performance will result. When both problems cannot satisfactorily be addressed statically, we propose to partition the program dynamically based on the given data decomposition. It is this concept that forms the basis of what we call memory-centric architectures. We have proposed two such architectures; DataScalar and DDT. DataScalar architectures use massively redundant computation to improve communication performance. in a DataScalar architecture, physical memory is divided into distinct regions, each of which is coupled with a processor. The second memory-centric architecture that we describe here is called DDT, for Dynamic Data Threads. In a DDT machine, the memory is distributed among multiple processors, as with a DataScalar architecture, but computation along a local dependence chain occurs uniquely at one node.