Analysis and verification of board power delivery network impact on DDR3L memory interface in ARM SoC application

In this paper, a DDR3L simulation topology for ARM SoC application is presented and the impact of the board power delivery network (PDN) on a DDR3L memory interface is simulated and analyzed. The analysis of the DDR3L PDN of the package and board will be discussed in the frequency-domain while the DDR power noise and DDR3L data signals are analyzed in the time-domain. A timing jitter comparison of the measured and simulated eye-diagram is presented. Finally, the analysis verifies the importance of including the board PDN to accurately predict the performance of the DDR3L memory interface in the simulation and modeling environment.