On-chip measurement and characterization for high-speed links

Today's high-speed interface designers are facing increasingly complex challenges imposed by the requirements of high performance, optimal power efficiency, and often by tight 3-D integration, such as in package-on-package (PoP) systems. Answers to many difficult, yet critical questions, need to be found by measurement inside the high-speed interfaces. What is the signal quality after the package pin and equalization circuitry? What is the relative jitter impact with clock-data-recovery (CDR) on versus off? What is the actual dynamic supply noise experienced by the various sections of the on-chip circuitry? What is the power delivery network (PDN) impedance seen from the silicon? Conventional off-chip probing at the board- or package-pin-level is neither sufficient nor relevant to answer these questions. On-chip signal integrity (SI) and power integrity (PI) characterization techniques are therefore indispensable. This tutorial first gives an overview of on-chip SI/PI measurement requirements. It then reviews several key on-chip measurement concepts and techniques to allow true on-chip SI/PI characterization: • eScope for measuring operating voltage and timing margin of the entire link • eWave for capturing equivalent-time signal waveform as seen by the actual data sampler • nScope for monitoring on-chip power supply noise • zScope for characterizing on-chip self and mutual PDN impedances Application examples for both parallel and serial interfaces will be discussed, including low-power memory interfaces and Serializer/Deserializer (SerDes) links.