Wafer warpage in FO-WLP — Making friends out of enemies

With technology related shrink and ever increasing functionality being included in individual semiconductor dies, dies are becoming smaller with an ever increasing number of I/Os. These two facts are accelerating migration to FanOut wafer level packaging whilst the increased number of I/Os with reduced die pad pitch is forcing the use of multiple redistribution layers. The flexibility of the eWLB Fan Out wafer level packaging technology also allows a simple conversion from leadframe based packages such as QFN packages by simulation of the pad layout and footprint in the redistribution layer. The topography of many FE dies obliges the use of thicker dielectric layers to guarantee a successful and effective coating. Depending on the chemical nature of the dielectric used the stresses produced by chemical shrinkage during curing can induce high levels of wafer and component level warpage in relatively flexible eWLB wafers particularly under conditions of low silicon occupation. This is further enhanced as one increases the number of dielectric layers and when more than one tensile seedlayer is deposited for a second electroplated Redistribution Layer. The aim of this paper is to introduce techniques used to balance the stresses within eWLB wafers and singulated components to achieve processability in 300mm multi-layer eWLB. Equilibrium must be found between mold cure, wafer expansion and dielectric cure in order to produce wafers which are sufficiently planar to pass through a single layer plus UBM process. Methods used, such as silicon to volume ratio tuning and cure regime adjustment have been characterized in terms of wafer warpage, along the process. The data shown will be for both a 1-layer plus UBM eWLB test vehicle with the original low temperature cure dielectric and an enhanced reliability higher temperature die