A low-power 77 GHz transceiver for automotive radar system in 65 nm CMOS technology

A fully-integrated low power 77 GHz radar transceiver in 65 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer based on a tripler. The receiver front-end provides a conversion gain of 21 dB, and the PA has an output power over 10 dBm. The phase noise of VCO is -75 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 217 mW and the size of the chip is 0.8 × 1.1 mm
²
.