An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS

A low-power 14-bit 150MS/s pipelined ADC is presented. This prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. Range-scaling in the first stage enables a maximal 2V
_p-p
input signal swing with a power-efficient single-stage opamp. Opamp and capacitor sharing between the first and second stage reduces the opamp power consumption further. And the sample-and-hold amplifier (SHA)-less technique is also used to lower the power dissipation and noise. With digital calibration, the SNDR of the ADC is 71.3dB with a 2.4MHz input, and remains higher than 68dB for input frequencies up to 150MHz. The ADC consumes 85mW, which includes 57mW for the ADC core, 11mW for the low jitter clock receiver and 17mW for the high-speed reference buffer.