A high-level synthesis and verification tool for application specific kth Root Processing Engine

Implementation of division, square root, and cube root and their inverses at the hardware level creates a number of bottlenecks in terms of accuracy, speed and design verification in particular. There are many DSP and communication systems in which these arithmetic operations are used. Therefore, a Newton-Raphson algorithm based, efficient, accurate and reconfigurable k
^th
root design and verification system is introduced. The design and verification system generates Verilog HDL design code and required control signals for application-specific operations. The design can be used for multi-purpose arithmetic operations based on an assigned k value, such as division for k=1, square root for k=2, cube root for k=3 and so on. The generated hardware can be used as a standalone design or can be implemented into a larger system by using a hand shake signal, which could make this design and verification tool suitable for new or ongoing projects. This tool generates Verilog RTL code and its testbench that can be implemented in FPGAs and VLSI systems. The proposed design tool can increase productivity by reducing design and verification time. Several case studies have been implemented on Xilinx Virtex-5 FPGAs. The designed system uses MATLAB-based verification and reporting for fast and accurate design evaluation.