High performance architecture for the encoder of JPEG-LS on SOPC platform

JPEG-LS is the latest coding standard for lossless and near-lossless still image compression issued by ITU/ISO. In this paper, a high performance encoder architecture for the regular mode in the lossless scheme of JPEG-LS is proposed and implemented on an ALTERA SOPC platform. The encoder is designed in a fully pipelined architecture with thirteen stages. The proposed encoder architecture can have a clock rate up to 113.03MHz, and with a throughput up to 113.03MPixel/s. It is noted that, the proposed pipelined encoder architecture is known to have the most stages when compared with all other JPEG-LS encoders. Moreover, the final stage of the proposed encoder can have the generated variable-length codewords packed in one group every 32bits so that the encoded bitstream can be stored in memory with a more efficient manner. As we will see in the experiment, the proposed architecture can have a very good performance in terms of throughput, chip area, memory usage, and outperforms existing state-of-the-art JPEG-LS encoders.