Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at higher voltage and temperature. Design is implemented in CMOS 32NM low power technology for dual port (DP) SRAM bit cell 0.390u2 (DP390) having a normal operating range from 0.9 to 1.1 V, extended to 0.75–1.1 V by utilizing proposed WA circuit. This design has an area overhead of 4.5%. Write cycle performance improvement and dynamic power reduction achieved is 10% and 8%, respectively, at 0.9 V with respect to the design without WA.