A low noise preamplifier and switched capacitor filter for heart-rate detection

The development of deep-submicron CMOS IC fabrication technologies has brought portable, battery operated devices such as cardiac pacemakers and personal heart rate detectors to the market. This paper presents a 1.8 V analog front-end for heart-rate detector. The front-end includes cascaded preamplifier and filter designed to reduce the device flicker noise at ECG bandwidth. The sensed low amplitude ECG signal from a noisy environment is amplified by the preamplifier. Special feedback mechanism has been employed to increase the SNR against body-electrode source noise. The designed preamplifier is reported to achieve a SFDR (Spurious free dynamic range) of 87.5 dB with a total power consumption of 0.354 mW combined with the filter. The current design is carried out using BSIM3V3.2 model at 0.18 μm UMC process technology.