Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V
DD
scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners and temperature with appropriate body bias selection. DDC technology also increases SRAM static noise margin (SNM) reduces 8Mb V
DDmin
by 150 mV reduces SRAM active leakage by 50% while maintaining Iread and reduces SRAM retention leakage by 5x.