A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure

We developed a high density 1R/1W SRAM macro based on 8T-SRAM with an effective scheme for Design for Testability. To achieve a smaller Macro area, a differential sense amplifier is introduced to read the data, where the reference voltage for reading 0/1 data is generated by unselected cell array. In addition, we proposed a screening test circuit for read disturb operation. A 512 kbit two port SRAM macro based upon 28nm process was designed, confirming experimentally that the worst minimum operation voltage (Vmin) can be reproduced by our test circuit. The bit density of 3.16 Mb/mm
²
was achieved, which is the highest among recent literatures.