Logic synthesis for manufacturability considering regularity and lithography printability

This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different levels of regularity and different area overheads during the logic synthesis, in order to improve overall design yield. A technology remapping tool with such yield model as cost function is proposed and implemented and interesting results are presented.