Parasitic modeling for accurate inductive switching simulation of converters using SiC devices

In this paper, the parasitic inductances for inductive switching of SiC devices in a switching converter were modeled and analyzed using a 3-D inductance extraction program. A double pulse test-bench was built to characterize the resistive and inductive switching behavior of the SiC devices. In order to capture the parasitic ringing in the fast switching transient, the gate-to-source switching loop and drain-to-source switching loop parasitic inductances of the PCB layout are extracted by the 3D inductance extraction program. The system model in Pspice includes SiC device models and the extracted parasitic elements. Simulation results are compared with experimental results. The comparison shows good agreement between simulation and experimental results under both resistive and inductive switching conditions.