Gate CD control for a 0.35 /spl mu/m logic technology

To meet the demand for increased microprocessor performance while minimizing the loss due to excessively hot transistors, a comprehensive lithography methodology was implemented for improved gate CD control. Reduction in lot-to-lot CD variability was achieved by linking resist coaters, steppers, and developers into cells and through freezing of the process. Critical parameters were identified and monitored through SPC. A closed-loop system involving lithography and etch personnel provided added feedback on the lithography process control. The methodologies described in this paper led to improved gate-CD control with less than /spl plusmn/0.020 /spl mu/m variability.