0.25 /spl mu/m integrated circuit yield model design and validation

This paper provides an overview of the design and the methods used to establish validated defect density targets for a 0.25 /spl mu/m process tool set based on a new SEMATECH yield model. This is the first model to provide industry tool targets derived from real manufacturing data. Besides the model design and the model validation approach, the paper provides particles per wafer pass (PWP) tool targets (for top ten yield detractors) to achieve 90%, random defect limited yield (RDLY) for a 0.25 /spl mu/m logic process. Future work to optimize the model further is outlined as well.