Timing-constrained minimum area/power FPGA memory mapping

Physical block memory is one of the earliest hardened blocks in modern FPGAs. FPGA memory mapping utilizes memory blocks to construct user's logic memory designs. Previous mapping methods optimized for circuit area or power consumption. However, timing performance becomes more important for large and critical logic memory designs. In this work, a critical path delay model will be presented for the first time to estimate implementation performance during memory mapping. Experiment results showed that over 90% estimation errors by the model were within 10% and the average was only 3.5%. Based on the delay model, we proposed the first timing-constrained FPGA memory mapping algorithm. The algorithm generates memory configurations that meet the user's performance requirement. The algorithm also achieves optimal area/power subject to the user's timing constraint. The area or power optimum was validated with a commercial FPGA memory mapper.